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COREsim

The addition of discrete event simulation capability to CORE with the COREsim option allows execution of the integrated architecture by dynamically interpreting the behavior model that resides in the system design repository. Discrete-event simulation logic identifies timing, resource utilization, and model inconsistency including:

• Timeline Analysis - COREsim timeline analysis identifies the sequential and concurrent events that occur during the simulation based upon data triggers, resource availability, random probabilities, and outcomes.
• Resource Analysis - COREsim resource analysis monitors resource availability to identify bottlenecks, resource contention, and queuing effects on system performance.
• Consistency Analysis - COREsim may be used interactively to identify logical inconsistencies as the behavioral model is developed. This provides the engineer with a dynamic modeling construction kit for establishing a complete and logically consistent model of system behavior.